A basic operation of a DRAM is to allow a user to change the electrical information stored in its memory arrays. FIG. 1 is a general illustration of a typical 5 volt DRAM 10, including the following elements: Column decoding circuitry 12, a first half of a memory array 14, an N-channel sense amplifier (NSA) 16, a second half of a memory array 18, and a P-channel sense amplifier (PSA) 20. One skilled in the art will note that the DRAM is symmetrically oriented with the column decode in the center.
Concurring a read operation, and in reference to FIGS. 1 and 2, the column decode 12 routs signals going to and from the memory arrays. When a memory cell is accessed, or to be read, the word line (row line) is turned on, thus selecting the cell to be read and thereby dumping the stored charge of the cell onto the associated digit line. The small charge from the cell will cause a small voltage change on the digit line; either up or down depending whether a one or zero is stored. FIG. 2 illustrates when a ones charge is accessed from the cell. NSA will pull the lower voltage digit line towards ground, this is followed by PSA pulling the corresponding higher voltage digit line up, towards supply voltage (Vcc). The PSA and NSA amplify the voltage differences between the two digit lines associated with a particular memory cell being accessed.
After a read sequence, a write operation takes place. For the sake of simplicity, the operation of writing back a same signal to the memory cell will not be discussed. The more difficult write operation exists when an opposite signal must be written back and stored into the accessed memory cell. This operation involves the switching of the voltages on the two digit lines as illustrated.
Typically, the PSA is turned off during a write back to allow the high digit line to be pulled towards ground and the low voltage digit line to be pulled up towards a ones voltage level. Thereafter attaining a write back, PSA is turned back on to continue recharging the new digit line towards the ones voltage level. Whereby, the respective voltages on the digit lines are clamped, trapping the appropriate charges in the memory cells, and the high and low voltages are equilibrated together to provide for an intermediate per-charged voltage level in preparation for the next cycle.
One skilled in the art will realize why the PSA is turned off during the write operation. Specifically, this allows the switching of the voltages on the digit lines without fighting the effort of the PSA to keep the high voltage digit line at a high voltage.